This invention relates to a semiconductor apparatus and the method of manufacturing the same and, more particularly, to a technique of isolating a semiconductor element formed on a semiconductor substrate.
The LOCOS (Local Oxidation of Silicon) method is widely known as a technique of isolating a semiconductor element. The LOCOS method consists in depositing an acidproof layer, for example, a silicon nitride layer (SiN.sub.3 layer) on a semiconductor substrate with an insulation layer interposed therebetween, patterning the silicon nitride layer (SiN.sub.3), and forming a thick, semiconductor element-isolating insulation layer by selective oxidation with the silicon nitride layer used as a mask. However, the LOCOS method has a drawback that dimensional errors arise between the width of the selective oxidation mask (silicon nitride layer) and that of the semiconductor-isolating region. Assume, for example, that the silicon nitride layer has a thickness of 2500 .ANG., an insulation layer (a silicon oxide layer) interposed between the semiconductor substrate (silicon substrate) and the silicon nitride layer has a thickness of 1500 .ANG., a semiconductor element-isolating insulation layer, when oxidized, has a thickness of 8000 .ANG., and the finished insulation layer for the isolation of a semiconductor element has a thickness of 5000-6000 .ANG.. Then the above-mentioned dimensional error ranges between 0.8 to 1.6 microns. Thus, for an insulation layer for which adequately isolates the elements and which is formed by the LOCOS method, the practical width of a semiconductor element-isolating region is limited to about 2.0 microns. The LOCOS method, however, cannot isolate a semiconductor element finer than the limit width of about 2.0 microns.
It has been experimentally confirmed that a certain relationship exists between the width of a semiconductor element-isolating region and the thickness of an insulation layer applied for the isolation of the semiconductor element. When the semiconductor element-isolating region is reduced in width, the insulation layer becomes thinner, thereby presenting difficulties in ensuring the electrically sufficient property of isolating a semiconductor element. Now let it be assumed that a semiconductor element-isolating insulating layer finished under the aforementioned conditions has a width of 1.4 microns. Then, with the occurrence of crystal defects in the semiconductor substrate taken into account, the finished semiconductor element-isolating insulation layer has a thickness approximately ranging between 3000 and 3200 .ANG.. Thus, is difficult to obtain a semiconductor element-isolating insulation layer having a greater thickness than that level.
Further it should be noted that the thickness of the semiconductor element-isolating insulation layer is determined by the relationship between the thickness and the impurity concentration of a conductivity reversion-preventing layer underlying the insulation layer. The higher the impurity concentration, the thicker the resultant semiconductor element-isolating insulation layer. If, however, the conductivity reversion-preventing layer is doped with an impurity in an indiscriminately high concentration, an electrical effect between semiconductor occurs and in operation speed of semiconductor elements will decrease, presenting disadvantages in the manufacture of semiconductor elements.
As described above, the conventional, semiconductor apparatus-manufacturing method involving the formation of a semiconductor element-isolating insulation layer by the LOCOS method has the drawbacks that noticeable dimensional errors arise. Furthermore, it is impossible to form a thick semiconductor element-isolating insulation layer in a narrow region wherein the adjacent semiconductor elements are to be isolated from each other.